The invention relates to a telecommunication device, more particularly, a mobile radio terminal, comprising at least one processor for processing data, to which processor at least one data memory is assigned which is coupled to the processor via data and address lines of a bus system.
In processor-controlled telecommunication devices, processors and data memories are coupled to each other by bus systems which have a certain number of data lines and address lines depending on the system configuration. The bus systems also have control lines over which control signals are exchanged between the processors and the data memories. For example, microprocessors or signal processors are used as processors here. Examples for data memories used are RAM, ROM, EPROM and Flash EPROM. One processor may be assigned various data memories to which the processor has access. For loading data of a data memory, the respective processor applies addresses to the address lines of the bus system and transmits them to the data memory. The data memory then transmits the associated data over the data lines of the bus system to the processor. The addressing over the data lines of the bus system is effected at the cost of a power consumption that is considerable for many applications. The power consumption, especially in telecommunication devices using a battery or an accumulator as an energy source, is a critical magnitude (for example, for mobile terminals). Furthermore, the addressing over data bus address lines leads to certain minimum data memory access times of a processor, so that the speed with which the program runs can be carried out by the processor is restricted accordingly.